• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An image capture method in an active pixel array and pixel array image sensor, fed between a first zero potential power supply terminal (Vss) and a second power supply terminal Positive supply potential (Vdd). Each pixel comprises a photodiode and a gate for transferring the photogenerated charges to a charge storage node. The transfer gate is carried by a charge pump at a negative potential (VNEG) during the charge integration time and receives a transfer control signal (TRA) common to all the pixels during a transfer time window. The transfer or reset control signal comprises successively at least a first phase during which it passes from negative potential (VNEG) to a positive transfer potential, a second phase during which it switches from positive transfer potential to zero potential provided by the first power supply terminal, a third phase of finite duration during which it remains at zero potential, and a fourth phase in which it goes from zero potential to negative potential provided by the charge pump. The fact of going through the supply potential limits the current calls in the charge pump which must restore the negative potential VNEG at the end of the transfer.
    公开号:FR3018653A1
    申请号:FR1451974
    申请日:2014-03-11
    公开日:2015-09-18
    发明作者:Frederic Barbier
    申请人:e2v Semiconductors SAS；
    IPC主号:
    专利说明:

    [0001] The invention relates to active pixel electronic image sensors. These sensors use a network of pixels in rows and columns, with in each pixel a photosensitive element and several transistors. An advantageous constitution of the pixel is a constitution as represented in FIG. 1, with: a self-polarized photodiode PH (pinned photodiode), a charge storage node ND, which is the equivalent of a capacitance a transfer transistor T1 for isolating the photodiode from the storage node or, on the contrary, allowing charge transfer from the photodiode to the storage node in order to measure the potential of the storage node after this transfer, a transistor T2 load sensing circuit, mounted as a voltage follower, having its gate connected to the storage node to enable the potential of the storage node to be returned to the source of the transistor, - a resetting transistor T3 of the storage node, for carrying to a reference value the potential of the storage node for measuring this reference potential, with a view to a differential measurement of the potentials of the storage node in the presence of charges iss of the photodiode and in the absence of charges from the photodiode; a pixel selection transistor T4, controlled by an on-line addressing SEL conductor, for transferring the potential of the source of the read transistor T2 to a column conductor COL; the line conductor SEL is common to all the pixels of the same pixel line; the column conductor COL is common to all the pixels of one and the same column of pixels, and finally, optionally, an additional transistor T5 which may have one and / or the other of the following two functions: evacuate towards a drain anti-glare electrical charges in excess in the photodiode in case of too strong illumination, or reset the potential of the photodiode by emptying completely to a drain the accumulated charges so that it can resume its empty potential before starting a new integration period; the transistor T5 is optional and makes it possible to define a start of integration time common to all the pixels. It will be noted that the term "transistor" is used to facilitate understanding in terms of electrical diagram such as the diagram of FIG. 1. However, in the physical constitution of the pixel, these transistors are not necessarily constituted in a conventional manner, independently of the other elements of the pixel, with a source region, a drain region, a channel region separating the source of the drain and an insulated gate above the channel. In the actual physical constitution of the pixel, some transistors are in fact essentially constituted by an insulated gate to which a control potential can be applied. Thus, for example, the transfer transistor T1 is constituted by an isolated transfer gate of the substrate, surmounting a region which is situated between the photodiode PH and an N + type diffusion constituting the charge storage node; the source of the transistor T1 is the photodiode; the transistor drain is the charge storage node. Similarly, the transistor T5 is formed from an insulated gate, adjacent on one side to the photodiode (constituting the source of the transistor), on the other to a drain for discharging charges (constituting the drain of the transistor ).
    [0002] In the sensors of the prior art, it has been demonstrated the existence of what is generally called a dark current, that is to say a parasitic charge flow even in the absence of illumination , while the absence of illumination should result in an absence of charges. These parasitic charges reduce the signal-to-noise ratio and are particularly harmful when measuring low light levels. Part of the dark current is due to the interface defects between the N-region of the photodiode and an insulating silicon oxide that surrounds the photodiode to isolate it from neighboring photodiodes. This insulating oxide, generally known as STI, of the English "Shallow Trench Isolation", is contained in a superficial trench which surrounds the entire photodiode with the exception of the passage which must be reserved to transfer the charges. from the photodiode (transistor T1) to the storage node and with the exception of the passage that must possibly be reserved to empty the charges of the photodiode during a reset (transistor T5). Interface faults trap electrons; these electrons are then released and attracted to the storage node at the moment of charge transfer from the photodiode to the storage node; they will therefore be considered useful payloads resulting from illumination whereas they are in reality parasite charges not resulting from illumination. To best limit this effect, it has already been proposed to interpose between the photodiode region (N-type) and the trench filled with insulator, a P-type region. This P region is in contact with the active silicon layer. of type P in which the photodiode is formed. It surrounds the N region of the photodiode and prevents the photodiode from being in direct contact with the insulating trench. It serves as a passivation layer that reacts with the insulating trench to neutralize parasitic charges. However, it is not possible, in an industrial process, to place a P-type region under the gates (which are polycrystalline silicon) of the transfer transistor T1 or the transistor T5 when present; the reason is that the implantation type P must in practice be made after the establishment of the grids and so we can not implement a type of impurity P under the grids; the silicon oxide insulation trenches nevertheless extend under the gates and it would have been preferable to pass them by a region P there as elsewhere. Consequently, the semiconductor regions under the gates of transistors T1 and T5 remain in direct contact with silicon oxide and are capable of generating a harmful dark current, on the principle of what has been explained hereinafter. above. The gate of the transfer transistor T1 could be maintained at a low negative potential (about -0.7 volts) instead of a zero potential during the integration of photogenerated charges. This tension would attract and accumulate holes under the grid; the electrons trapped at the oxide / silicon interface then recombine with these mobile holes and disappear, eliminating the risk of unwanted electrons moving towards the storage node during charge transfer from the photodiode to the storage node. But to produce this negative voltage, while the integrated circuit is powered between 0 volts and a positive voltage of 3 to 5 volts, it is necessary to use a charge pump. Charge pumps have a low efficiency, less than 50% and sometimes even less than 30%. They consume a much higher current than they must provide. In a mode of operation of the so-called "global shutter" sensor, that is to say with overall exposure time, the transfer phase is simultaneous for all the pixels of the sensor. All the pixel array transfer grids are operated at the same time to transfer the photodiode charges to the storage nodes. For a sensor of 2 million pixels the current draw in the charge pump to return to a potential of -0.7 volts at the moment when the transfer pulse ends can exceed 80 milliamperes, and that on condition of doing so that the descent time of the control pulse is forced to at least 300 nanoseconds so that the transition is not too abrupt. The 80 milliamps provided by the charge pump to discharge the equivalent capacity of all parallel connected transfer grids can result in an overall consumption of 250 milliamps due to the low efficiency of the charge pump. To solve the problem of the dark current without creating a very high current draw difficulty when switching the transfer gate from the high state to the low state or vice versa, the invention proposes to carry out this switching to the low state in three distinct times which is a transition from a positive voltage to zero (potential of a power supply terminal of the sensor) then a stabilization to zero, then a transition from zero to a negative voltage supplied by a charge pump. Most of the charges accumulated in the transfer gate during the transfer pulse then discharge first into the supply terminal at zero volts (ground) and not into the charge pump; this only ensures the transition of the gates of the transfer transistors from 0 volts to the low negative voltage (-0.7 volts for example). Therefore, the invention proposes a method of image capture in a d active pixel line array and column image fed between a first zero potential power terminal and a second power supply terminal at a positive power potential, wherein each pixel has a photodiode formed in an active layer semiconductor to the zero reference potential, a charge transfer gate for transferring the charges generated by the light of the photodiode to a charge storage node, and possibly a potential reset gate of the photodiode, the method comprising a step of overall charge transfer of the photodiodes of all the pixels of the array to the corresponding storage nodes and possibly a reset step isation of all photodiodes, characterized in that the transfer gate and / or the reset gate is carried by a charge pump at a negative potential for most of the charge integration time and receives a control signal transfer or reset common to all the pixels during a transfer time window, the transfer or reset control signal comprising successively at least a first phase during which it passes from negative potential to a positive transfer potential, a second phase during which it switches from positive transfer potential to zero potential provided by the first power supply terminal, a third phase of finite duration during which it remains at zero potential, and a fourth phase in which it goes from zero potential to negative potential provided by the charge pump.
    [0003] The charge pump serves to maintain the negative potential during the integration period, but it does not undergo a strong current draw in this phase. It is not used during the second and third phases. Then, it is used to change the potential from zero to the negative potential at the end of the transfer control signal, but the potential difference is then smaller than the difference between the positive potential of the first phase and the final negative potential. The current draw due to the capacitive discharge is reduced accordingly. The gain on the current draw is in the ratio of these two voltage differences.
    [0004] For example, the positive potential is 3.3 volts and the negative potential is -0.7 volts. The gain in consumption is in the ratio 4 volts / 0.7 volts is about 5.7. The transition from the positive potential to the zero potential is not made by the charge pump, but the capacitive discharge current flows directly into the supply terminal at the zero potential. The low efficiency of the charge pump does not intervene in this phase. In one embodiment, only the descent of the transfer pulse (or reset) undergoes a phase of passage through the zero potential provided directly by the first power supply terminal. In another embodiment, for reasons of symmetry, the same form is given to the rise of the transfer pulse, with a phase of rise of the negative potential supplied by the charge pump to the zero potential supplied by the first terminal of power supply, a phase of finite duration at this potential, and a phase of rise of the potential from zero to the positive potential which ensures the transfer of charges. Sensors contemplating applying a negative voltage to the transfer gate are described in the following publications: US2008296630, US 8, 163,591, US 2009/0219418, and Bongki Mheen, Young-Joo Song, and Albert JP Theuwissen, Negative. Offset Operation of Four-Transistor CMOS Image Pixel for Increased Well Capacity and Suppressed Dark Current. Other features and advantages of the invention will appear on reading the detailed description which follows and which is given with reference to the appended drawings in which: FIG. 1, already described, represents a conventional pixel electrical diagram at five transistors; FIG. 2 represents a time diagram of the general operation of the pixel; FIGS. 3A and 3B show a possible example of a form according to the invention of control pulses for transferring or resetting the photodiodes; FIGS. 4A and 4B show theoretical forms of control pulses for transferring or resetting the photodiodes according to the invention; FIGS. 5A and 5B show the actual shape of the control pulses, taking into account the recovery time of the charge pump; FIG. 6 represents a time diagram of the operation of the sensor according to the invention; FIG. 7 represents a circuit for generating the transfer or reset signal; FIG. 8 shows the signals used in the circuit of FIG. 7. In FIG. 2, the conventional operating timing diagram of a 5-transistor pixel using the fifth transistor is shown to trigger the start of the period of time. integration (operation in "global shutter" mode). Operation in "global shutter" mode would be possible in the absence of transistor T5, but the integration time would not be adjustable, it would be equal to the period FR. The operation is periodic with a frame period FR. The frame begins with a reset pulse GR applied to the gate of transistor T5 for all pixels at a time when such a transistor is provided. The impulse empties the charges that have been integrated by the light into the photodiodes. The end of the GR pulse marks the beginning of the integration time Ti, common to all the pixels. The end of this duration will be defined by the end of a transfer pulse TRA applied to the gate of the transfer transistor T1; this pulse, common to all the pixels in the global shutter mode, transfers the integrated charges of the photodiode to the storage node ND. During the integration time, before the TRA pulse, a reset potential level (RST line) is applied to the gate of the transistor T3 to empty the charges that may be contained in the storage node. This signal is necessarily interrupted before the transfer pulse.
    [0005] After the integration time Ti, the pixels are read line by line, a selection signal (line SEL) being applied successively to each of the lines to define the time of the reading. This signal is shown for a single line in Figure 2; it is applied to the gate of transistor T4. The reading is done in a reading circuit not shown, located at the foot of each column of pixels and connected to the respective COL column driver. The read circuit comprises in particular a sampling circuit controlled by pulses shs and shr for respectively sampling the useful potential level of the column conductor after the transfer pulse TRA and the potential level after reset. The measurement is made by difference between the two samples at each period. The reading phase for a given line, defined by the slot SEL applied to this line, successively comprises the emission of a sampling pulse shs, the emission on the gate of the transistor T3 of a reset pulse rst of the storage node of the pixels of the considered line, and the emission of a sampling pulse shr. The difference of the sampled signals is converted by an unrepresented analog-to-digital converter. In the prior art, the transfer signal TRA and the eventual reset signal GR for the photodiodes are common to all the pixels and are most often pulses starting from the zero volt reference voltage which is the potential of the active layer. semiconductor in which the photodiodes are formed; these pulses take a positive value for a short time and they allow the emptying of the charges stored in the photodiode. The transfer control or reset control signal then has the rectangular shape shown in FIG. 3A from zero to a positive transfer potential, which can be Vdd when the sensor is powered between two supply terminals Vss (zero) and Vdd positive. Vdd is typically 3.3 volts. As explained above, the shape of the pulses could be that of FIG. 3B if the control signal is maintained at a slightly negative voltage (of -0.7 volts for example) during the integration phase and if the rising and falling edges are forced to have a minimum duration to prevent strong current draws. The minimum duration of the edges is for example 300 nanoseconds and the total duration of the TRA or GR signal can be about 1 microsecond. According to the invention, the profile of the transfer control or reset signal is given a different shape, represented in FIG. 4A, which imposes a passage of the signal for a finite duration by the zero supply potential, between the moment when this signal is at its high positive level and the moment it returns to its negative low level. The transfer or reset control signal is therefore decomposed into at least a first phase during which it switches from negative potential to positive transfer potential (and is preferably maintained for a duration of a few hundred nanoseconds), a second phase during which it switches from the positive transfer potential to the zero potential provided by the first power supply terminal, a third phase of finite duration during which it remains at zero potential, and a fourth phase in which it goes back to zero potential to the negative potential provided by the charge pump. The hold time at zero potential can be short. It must be sufficient to allow zero discharge of the gate capacitances of all transistors in the array. A hundred nanoseconds is enough. Optionally, for reasons of symmetry and simplification of the formation of the signal, during the first phase, as shown in FIG. 4B, a passage through the zero supply potential is also imposed for a finite duration between when the signal is at its negative low level and the moment when it reaches its high positive level. A gradual rise slope up to the positive potential is preferably (but not necessarily) provided in the first phase to limit current draws; likewise, a progressive descent slope 30 is preferably provided from the positive potential in the second phase. The rising and falling edges can then last between 100 and 400 nanoseconds. A similar descent or climb gradient may also optionally be provided in the fourth phase (zero descent to 0.7 volts), as well as in the rise of the negative potential to the zero potential.
    [0006] The control signal forms shown in FIGS. 4A and 4B may be used for the transfer control signal TRA and for the reset control signal GR when a reset transistor T5 is provided and is activated to define the start of the duration 5 of integration. These forms can also be used for only one of these two signals, the other not having a maintenance phase at the zero supply potential. The signal forms shown in Figures 4A and 4B are theoretical forms shown to simplify the explanations. The actual shapes are rather those shown in FIGS. 5A and 5B as will be explained later, because the voltage produced by the charge pump (theoretically -0.7 volts, for example) of the charging takes a long time to regain its nominal value from the moment it goes into service. Figure 6 shows the general operating chronogram of the sensor. It is similar to that of FIG. 2 and the explanations are the same, the differences being as follows: the low potential of the signals TRA and GR (or at least one of the two) is here negative during the integration period of loads; and the form of the transfer control signal and the reset signal comprises, at least for the descent from the positive potential to the negative low potential, a plateau of finite (non-zero) duration at zero potential as described with reference to FIGS. 4A. and 4B. The duration of the transfer control (or reset) signal may be of the order of 1 millisecond. It should be noted that in the scheme of FIG. 6 the low potential of the transfer control signal is negative throughout the load integration period and remains low during the reading of the loads (i.e. during the signals Selection SEL of successive lines). However, as shown by a dotted line, the transfer control signal could be reset to zero potential during the read phases. The charge pump is not solicited during the reading, it does not bring spurious noise on the storage node, related to interference signals of high frequency switching of the pump. In FIG. 6 as in FIG. 2, only the salt and read selection signals shs, rst, shr are shown for a single line; these signals are repeated successively to ensure selection and reading for the different lines. FIG. 7 represents a circuit for controlling a line connecting the gates of the transfer transistors T1 of all the pixels of the same pixel line of the sensor. This circuit would be the same to control a line connecting the gates of the reset transistors T5 of a pixel line. Each control circuit essentially comprises a power amplifier AMP and an associated voltage selector. The amplifier AMP is capable of providing a load current of the gate capacitances of all the transistors of the line, typically a maximum current of 50 to 100 microamperes; the fact that the output current of the amplifier is limited defines a rise slope for the signal applied to the gates of the line; for example a current limited to 100 microamperes defines a rise or fall time of about 250 nanoseconds if the line capacity is 6 picofarads. The amplifier AMP is supplied between a high voltage VHI which may be the voltage Vdd (3.3 volts for example) supplied directly by a positive general power supply terminal of the sensor, and a low voltage VLO 20 which is supplied by the selector VLOSEL voltage. The voltage selector receives both the low supply potential Vss supplied by a general supply terminal at the zero potential, and a negative potential VNEG provided by a charge pump PCH; it provides at its output one or the other potentials Vss and VNEG according to the logic signal it receives on its control input d_VLO. The amplifier is thus powered between Vdd and Vss, therefore by the two power supply terminals, or between Vdd and VNEG, therefore between the positive power supply terminal and the output of the charge pump, depending on the high or low state. down respectively of the signal d_VLO. The charge pump is common to all control circuits if these circuits are each assigned to a respective line of pixels. The amplifier AMP also receives on its input a logic control pulse d_TRA, which is provided by a sequencer (not shown) which establishes the various cyclic operating signals of the sensor. The signal d_TRA represents the transfer order at the end of an integration time. Its value is a logical low level 0 throughout the integration period; it switches to high logic level 1 only during the total duration of the transfer signal shown in FIGS. 4A and 4B. When d_TRA is at the low level, the amplifier supplies at its output the voltage VLO, that is to say either Vss or VNEG. When d_TRA is at the logic high level, the amplifier supplies at its output the voltage VHI, that is to say Vdd. The same explanations apply for the GR signal. The sequencer also provides the logic signal d_VLO for controlling the voltage selector VLOSEL. When the d_VLO signal is low, the voltage selector supplies the VNEG negative voltage of -0.7 volts to the amplifier. When d_VLO is high, the selector provides Vss. Fig. 8 shows the control signals d_VLO and d_TRA, and the resultant transfer control signal TRA. When d_VLO and d_TRA are low, the charge pump supplies VNEG to the amplifier and the amplifier supplies VNEG to the gate line. This is the case throughout the integration period Ti. When d_VLO goes high, the amplifier receives the voltage Vss from the low supply terminal of the sensor. The amplifier provides Vss on its output. When d_TRA then goes to the logic high level, the output TRA of the amplifier goes to Vdd with a non-zero rise time defined by the maximum possibilities of supplying current output from the amplifier. TRA then remains at Vdd for the duration of the signal d_TRA. It goes down to the Vss level at the end of the d_TRA signal with a nonzero descent time defined by the maximum current absorbing capability of the amplifier. And finally, we see that the signal TRA slowly returns the negative voltage VNEG at the end of the signal d_VLO. This slow return is due to the fact that the voltage VNEG is supplied by the charge pump; this provides a voltage which only progressively reaches the negative nominal voltage required because it is loaded through all the amplifiers by all the gates of the sensor lines. If it is desired to accelerate the return of the negative voltage to its nominal value, for example -0.7 volts, it is possible to put in parallel with the charge pump PCH one or more other charge pumps which are not put into service. only if the voltage VNEG falls in absolute value beyond a limit value. The PCH main charge pump maintains -0.7 volts during the integration time, with the other pump (s) only running at the end of the d_VLO signal. The outputs of the charge pumps are paralleled. A voltage regulator placed at the output of the set in parallel compares the output voltage of the main charge pump with a set value. If the deviation is too large, the controller provides a commissioning signal for the auxiliary charge pumps.
    [0007] All that has just been said about the signal TRA with reference to FIGS. 7 and 8 is also applicable to the reset signal GR. If the transistor T5 must provide an anti-glare function during the integration time, it is desirable that the negative voltage applied to its gate during this time imposes in the semiconductor a potential barrier slightly lower than the potential barrier. created at the same time under the gate of the transfer transistor. This can be achieved by providing that the threshold voltage of transistor T5 is lower than the threshold voltage of transistor T1. This can be done by having for these two transistors different channel dopings, or different gate oxide thicknesses. It can also be provided that the negative voltage applied to the gate of the transistor T5 during the integration phase is slightly higher (less negative) than that applied to the gate of the transistor T1. But it can also be provided that the transistor T5 does not serve as an anti-glare transistor and that auxiliary anti-dazzle means are provided.
    权利要求:
    Claims (3)
    [0001]
    REVENDICATIONS1. An image capture method in an active pixel array and pixel array image sensor, fed between a first zero potential power supply terminal (Vss) and a second power supply terminal at a positive power supply potential (Vdd), wherein each pixel comprises a photodiode (PH) formed in a semiconductive active layer at the zero reference potential, a charge transfer gate (T1) for transferring the charges generated by the light of the photodiode to a node of charge storage (ND), and optionally a resetting gate (T5) of the potential of the photodiode, the method comprising a step of overall transfer of the charges of the photodiodes of all the pixels of the matrix to the corresponding storage nodes and possibly a step of resetting all the photodiodes, characterized in that the transfer gate and / or the reset gate is carried by a charge pump (PCH) at a negative potential (VNEG) for most of the charge integration time (Ti) and receives a transfer control signal (TRA) or reset signal (GR) common to all the pixels during a window time of transfer, the transfer control or reset signal successively comprising at least a first phase during which it passes from negative potential (VNEG) to a positive transfer potential, a second phase during which it switches from positive transfer potential to zero potential provided by the first power supply terminal, a third phase of finite duration during which it remains at the zero potential, and a fourth phase in which it goes from zero potential to negative potential provided by the charge pump.
    [0002]
    2. An image capture method according to claim 1, characterized in that during the rise of the negative potential to the positive potential, the rise of the transfer pulse is given the same shape as the descent, with a phase negative potential rise of the charge pump at the zero potential provided by the first supply terminal, a phase of finite duration at this potential, and a phase of zero potential at the positive potential which provides the charge transfer.
    [0003]
    An image capture method according to one of claims 1 and 2, characterized in that the charge pump which operates to maintain a negative voltage during the integration time is assisted by at least one auxiliary charge pump. commissioning at the end of the charge transfer pulse or the reset pulse.
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1451974A|FR3018653B1|2014-03-11|2014-03-11|IMAGE CAPTURE METHOD WITH DARK CURRENT REDUCTION AND LOW CONSUMPTION|FR1451974A| FR3018653B1|2014-03-11|2014-03-11|IMAGE CAPTURE METHOD WITH DARK CURRENT REDUCTION AND LOW CONSUMPTION|
    JP2016556730A| JP6598791B2|2014-03-11|2015-03-05|Method for imaging with dark current reduction and low power consumption|
    CN201580013047.4A| CN106105181B|2014-03-11|2015-03-05|Image capturing method with reduced dark current and low power consumption|
    ES15707684T| ES2844206T3|2014-03-11|2015-03-05|Low power consumption dark current reduction imaging procedure|
    PCT/EP2015/054651| WO2015135836A1|2014-03-11|2015-03-05|Method of image capture with reduction of dark current and low consumption|
    US15/124,894| US10044934B2|2014-03-11|2015-03-05|Method for capturing an image with dark current reduction and low power consumption|
    EP15707684.5A| EP3117599B1|2014-03-11|2015-03-05|Method of image capture with reduction of dark current and low consumption|
    TW104107400A| TWI670976B|2014-03-11|2015-03-09|Method for capturing an image with dark current reduction and low power consumption|
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